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? semiconductor components industries, llc, 2002 may, 2002 rev. 1 1 publication order number: nb100lvep224/d nb100lvep224 product preview 2.5v/3.3v 1:24 differential ecl/pecl clock driver with clock select and output enable the nb100lvep224 is a low skew 1to24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. the part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. the two clock inputs are differential ecl/pecl and they are selected by the clk_sel pin. to avoid generation of a runt clock pulse when the device is enabled/disabled, the output enable (oe ) is synchronous ensuring the outputs will only be enabled/disabled when they are already in low state (see figure 4). the nb100lvep224 guarantees low outputtooutput skew. the optimal design, layout, and processing minimize skew within a device and from lot to lot. the nb100lvep224, as with most other ecl devices, can be operated from a positive v cc supply in lvpecl mode. this allows the lvep224 to be used for high performance clock distribution in +3.3 v or +2.5 v systems. singleended clk input operation is limited to a v cc 3.0 v in lvpecl mode, or v ee 3.0 v in necl mode. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. for more information on pecl terminations, designers should refer to application note and8020/d. ? 15 ps typical outputtooutput skew ? 85 ps typical devic etodevice skew ? maximum frequency > 1 ghz ? 575 ps typical propagation delay ? lvpecl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 2.375 v to 3.8 v ? internal input pulldown resistors ? q output will default low with inputs open or at v ee ? thermally enhanced 64lead lqfp this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. 64lead lqfp case 848g thermally enhanced fa suffix device package shipping ordering information nb100lvep224fa lqfp64 160 units/tray nb100lvep224far2 lqfp64 1500/tape & reel marking diagram* *for additional information, see application note and8002/d a = assembly location wl = wafer lot yy = year ww = work week nb100 lvep224 awlyyww 64 1 64 1 http://onsemi.com
nb100lvep224 http://onsemi.com 2 49 50 51 52 53 54 55 56 31 30 29 28 27 26 25 12345678 48 47 46 45 44 43 42 41 32 all v cc , v cco , and v ee pins must be externally connected to appropriate power supply to guarantee proper operation. the thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heatsinking conduit, capable of tran sfer- ring 1.2 watts. this exposed pad is electrically connected to v ee internally. function table oe (1) l l h h pin description function ecl differential input clock ecl differential input clock ecl input clk select ecl output enable ecl differential outputs positive supply negative supply pin clk0*, clk0 ** clk1*, clk1 ** clk_sel* oe * q0q23, q0 q23 v cc , v cco v ee *** figure 1. 64lead lqfp pinout (top view) v cco clk0 clk0 clk_sel clk1 clk1 v ee oe v ee v ee q8 q8 q9 q9 q10 q10 q7 v cco q7 q6 q6 q5 q1 v cco v cco q15 q15 q16 q16 q17 q17 v cco clk_sel l h l h q0q23 q0q23 clk0 clk1 l l clk0 clk1 h h 1. the oe (output enable) signal is synchronized with the falling edge of the lvpecl_clk signal. nb100lvep224 * pins will default low when left open. ** pins will default high when left open. *** the thermally conductive exposed pad on the bottom of the package is electrically connected to v ee internally. 9 10111213141516 q0 q0 v cc q23 q23 v cco q22 q22 q18 q18 q19 q19 q20 q20 q21 q21 23 22 21 20 19 18 17 24 40 39 38 37 36 35 34 33 57 58 59 60 61 62 63 64 q11 q11 q12 q12 q13 q13 q14 q14 q5 q4 q4 q3 q3 q2 q2 q1
nb100lvep224 http://onsemi.com 3 0 1 figure 2. logic diagram clk_sel clk0 clk0 clk1 clk1 oe q0q23 q0q23 q d 24 24 v cc v ee attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity (note 1) level 3 flammability rating oxygen index ul 94 v0 @ 0.125 in 28 to 34 transistor count 654 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 to 0 6 to 0 v t a operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) (see application information) 0 lfpm 500 lfpm 64 lqfp 64 lqfp 35.6 30 c/w c/w q jc thermal resistance (junctiontocase) (see application information) 0 lfpm 500 lfpm 64 lqfp 64 lqfp 3.2 6.4 c/w c/w t sol wave solder < 2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
nb100lvep224 http://onsemi.com 4 lvpecl dc characteristics v cc = 3.3 v; v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 170 170 170 ma v oh output high voltage (note 4) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 4) 1355 1480 1695 1355 1480 1695 1355 1480 1695 mv v ih input high voltage (singleended) (note 5) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (singleended) (note 5) 1490 1675 1490 1675 1490 1675 mv v ihcmr input high voltage common mode range (differential) (note 6) (figure 5) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to 0.5 v. 4. all outputs loaded with 50 to v cc 2.0 v. 5. single ended input operation is limited v cc 3.0 v in lvpecl mode. 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. necl dc characteristics v cc = 0 v, v ee = 2.375 v to 3.8 v (note 7) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 170 170 170 ma v oh output high voltage (note 8) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 8) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (singleended) (note 9) 1165 880 1165 880 1165 880 mv v il input low voltage (singleended) (note 9) 1810 1625 1810 1625 1810 1625 mv v ihcmr input high voltage common mode range (differential) (note 10) (figure 5) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 150 0.5 150 0.5 150 a note: 100lvep circuits are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been e stablished. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintain ed. 7. input and output parameters vary 1:1 with v cc . 8. all outputs loaded with 50 w to v cc 2.0 v. 9. single ended input operation is limited v ee 3.0 v in necl mode. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep224 http://onsemi.com 5 ac characteristics v cc = 2.375 v to 3.8 v; v ee = 0 v (note 11) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v opp differential output voltage (figure 3) f out < 50 mhz f out < 0.8 ghz f out < 1.0 ghz 500 450 400 600 600 550 600 550 450 700 700 650 600 550 450 700 700 650 mv mv mv t plh t phl propagation delay (differential) clkxqx clk_selxqx 575 675 575 675 575 675 ps ps t skew withindevice skew (note 12) devicetodevice skew (note 13) 15 85 15 85 15 85 ps ps t jitter random clock jitter (figure 3) (rms) < 1 ps v pp input swing (differential) (note 15) (figure 5) 150 800 1200 150 800 1200 150 800 1200 mv t s oe set up time (note 14) 200 200 200 ps t h oe hold time 200 200 200 ps t r /t f output rise/fall time (20%80%) 160 160 160 ps 11. measured with pecl 750 mv source, 50% duty cycle clock source. all outputs loaded with 50 w to v cc 2 v. 12. skew is measured between outputs under identical transitions and conditions on any one device. 13. devicetodevice skew for identical transitions at identical v cc levels. 14. oe set up time is defined with respect to the falling edge of the clock. oe hightolow transition ensures outputs remain disabled during the next clock cycle. oe lowtohigh transition enables normal operation of the next input clock. 15. v pp is the differential input voltage swing required to maintain ac characteristics including t pd and devicetodevice skew. 0 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 figure 3. output frequency (f out ) versus output amplitude (v opp ) and random clock jitter (t jitter ) frequency (mhz) 1 2 3 4 5 6 7 8 v opp (mv) t jitter ps (rms) tbd
nb100lvep224 http://onsemi.com 6 figure 4. output enable (oe) timing diagram clk clk oe q q figure 5. lvpecl differential input levels v ih (diff) v il (diff) v ee v cc (lvpecl) v ihcmr v pp resource reference of application notes an1405 ecl clock distribution techniques and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices 16. for an updated list of application notes, please see our website at http://onsemi.com.
nb100lvep224 http://onsemi.com 7 applications information using the thermally enhanced package of the nb100lvep224 the nb100lvep224 uses a thermally enhanced 64lead lqfp package. the package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. this exposed metal pad will provide the low thermal impedance that supports the power consumption of the nb100lvep224 highspeed bipolar integrated circuit and will ease the power management task for the system design. in multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the nb100lvep224. the size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. however, the solderable area should be at least the same size and shape as the exposed pad on the package. direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. the thermal vias will connect the exposed pad of the package to internal copper planes of the board. the number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. the recommended thermal land design for nb100lvep224 applications on multilayer boards comprises a 4 x 4 thermal via array using a 1.2 mm pitch as shown in figure 6 providing an efficient heat removal path. figure 6. recommended thermal land pattern all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 the via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. solder wicking inside the via may result in voiding during the solder process and must be avoided. if the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. this will supply enough solder paste to fill those vias and not starve the solder joints. the attachment process for the exposed pad package is equivalent to standard surface mount packages. figure 7, arecommended solder mask openingso, shows a recommended solder mask opening with respect to a 4 x 4 thermal via array. because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in figure 7. for the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. figure 7. recommended solder mask openings all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 0.2 1.0 1.0 0.2 proper thermal management is critical for reliable system operation. this is especially true for highfanout and high output drive capability products. for thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: table 1. thermal resistance * lfpm ja c/w jc c/w 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * junction to ambient and junction to board, fourconductor layer test board (2s2p) per jesd 518 these recommendations are to be used as a guideline, only. it is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. the exposed pad of the nb100lvep224 package is electrically shorted to the substrate of the integrated circuit and v ee . the thermal land should be electrically connected to v ee .
nb100lvep224 http://onsemi.com 8 package dimensions lqfp fa suffix 64lead package case 848g02 issue a y notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: mm. 3. datum plane e" is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting plane. 4. datum x", y" and z" to be determined at datum plane datum e". 5. dimensions m and l to be determined at seating plane datum t". 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum pland e". 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum d dimension by more than 0.08 (0.003). dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). 8. exact shape of each corner is optional. dim a min max min max inches 10.00 bsc 0.394 bsc millimeters b 10.00 bsc 0.394 bsc c 1.35 1.45 0.053 0.057 d 0.17 0.27 0.007 0.011 f 0.45 0.75 0.018 0.030 g 0.50 bsc 0.020 bsc h 1.00 ref 0.039 bsc j 0.09 0.20 0.004 0.008 k 0.05 0.15 0.002 0.006 l 12.00 bsc 0.472 bsc m 12.00 bsc 0.472 bsc n 0.20 0.008 p 0 7 0 7 r 0 --- 0 --- s --- 1.60 --- 0.063 v w aa 0.17 0.23 0.007 0.009 ab 0.09 0.16 0.004 0.006 ac 0.08 --- 0.003 --- ad 0.08 --- 0.003 --- ae 4.50 4.78 0.180 0.188 0.05 (0.002) s 1 b b/2 16 17 32 33 48 49 64 x l l/2 z m m/2 a a/2 aj aj z 0.20 (0.008) t x-y 4 pl z 0.20 (0.008) e x-y t seating plane g/2 g 4 pl ag ag d 64 pl z 0.08 (0.003) m t x-y e 0.08 (0.003) t exposed pad view agag detail ah detail ah ???? ???? aa d ab j detail ajaj ref base metal plating z 0.08 (0.003) m y t-u s c k scale 1:1 v r w n f h p ac 0.25 gage plane 60 pl 1 16 17 32 33 48 49 64 ad --- --- 11 13 11 13 11 13 11 13 af 4.50 4.78 0.180 0.188 ae af
nb100lvep224 http://onsemi.com 9 notes
nb100lvep224 http://onsemi.com 10 notes
nb100lvep224 http://onsemi.com 11 notes
nb100lvep224 http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nb100lvep224/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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